Microprocessor And Interfacing

Any application of Microprocessor Based system Requires the transfer of data between external circuitry to the Microprocessor and Microprocessor to the External circuitry.

8255 is a programmable I/O device that acts as interface between peripheral devices and the microprocessor for parallel data transfer. 8255 PPI (programmable peripheral interface) is programmed in a way so as to have transfer of data in different conditions according to the need of the system. It is used to interface to the keyboard and a parallel printer port in PCs (usually as part of an integrated chipset).

Here is the description of each block in this diagram:

Three 8-bit IO ports PA, PB, PC.

PC has two 4-bit parts: PC upper (PCU) and PC lower (PCL), each can be set independently for I or O.

Data bus buffer:

It is used to connect the internal bus of 8255 with the system bus so as to establish proper interfacing between the two. The data bus buffer allows the read/write operation to be performed from/to the CPU.

The buffer allows the passing of data from CPU to ports or control register in case of write operation and from ports or status register to CPU in case of read operation.

Read/ Write control logic:

This unit manages the internal operations of the system. This unit holds the ability to control the transfer of data and control or status words both internally and externally.

Whenever there exists a need for data fetch then it accepts the address provided by the processor through the bus and immediately generates command to the 2 control groups for the particular operation.

Group A and Group B control:

These two groups are handled by the CPU and functions according to the command generated by the CPU. The CPU sends control words to the

group A and group B control and they in turn sends the appropriate command to their respective port.

Group A has the access of the port A and higher order bits of port C (i.e port C upper). While group B controls port B with the lower order bits of port C (i.e port C lower).

Pin Diagram of 8255 PPI:

D0-D7(Data Bus) – These are bidirectional, tri-state data bus lines are connected to the system data bus. They are used to transfer data and control word from microprocessor (8085) to 8255 or receive data or status word from 8255 to the 8085.

PA0-PA7(Port A) – These are 8 Bit bidirectional I/O pins used to send data to output device and to receive data from input device. It functions as an 8 Bit data output latch/buffer when used in output mode and as an 8 Bit data input latch/buffer when used in input mode.

PB0-PB7(Port B) – These are 8 Bit bidirectional I/O pins used to send data to output device and to receive data from input device. It functions as an 8 Bit data output latch/buffer when used in output mode and as an 8 Bit data input latch/buffer when used in input mode.

PC0-PC7(Port C) – These are 8 bit bidirectional I/O pins divided into two groups PCL (PC3-PC) and PCU (PC7-PC4).these groups can individually transfer data in or out when programmed for simple I/O, and used as handshake signals when programmed for handshake or bidirectional modes.

CS – It stands for chip select. A low signal at this pin shows the enabling of communication between the 8255 and the processor. More specifically we can say that the data transfer operation gets enabled by an active low signal at this pin.

RD – It is the signal used for read operation. A low signal at this pin shows that CPU is performing read operation at the ports or status word. Or we can say that 8255 is providing data or information to the CPU through data buffer.

WR – It shows write operation. A low signal at this pin allows the CPU to perform write operation over the ports or control register of 8255 using the data bus buffer.

A₀ and A₁– These are basically used to select the desired port among all the ports of the 8255 and it do so by forming conjunction with RD and WR. It forms connection with the LSB of the address bus.

CS	A₁	A₀	Result
0	0	0	PORT A
0	0	1	PORT B
0	1	0	PORT C
0	1	1	Control Register
1	X	X	No Selection

The table below shows the operation of the control signals:

A₁	A₀	RD	WR	CS	Result
0	0	0	1	0	Input Operation PORT A → Data Bus
0	1	0	1	0	PORT B → Data Bus
1	0	0	1	0	PORT C → Data Bus
0	0	1	0	0	Output Operation Data Bus → PORT A
0	1	1	0	0	Data Bus → PORT A
1	0	1	0	0	Data Bus → PORT B
1	1	1	0	0	Data Bus → Control Register

Reset – It is an active high signal that shows the resetting of the PPI. A high signal at this pin clears the control registers and the ports are set in the input mode. Initializing the ports to input mode is done to prevent circuit breakdown. As in case of reset condition, if the ports are initialized to output mode then there exist chances of destruction of 8255 along with the processor.

Operating Modes:

1. BSR Mode:

This mode is used to set or reset the bits of port C only, and selected when the most significant bit (D7) in the control register is 0.

Control Register is as follows:

This mode affects only one bit of port C at a time because, as user set the bit, it remains set until and unless user changes it. User needs to load the bit pattern in control register to change the bit.

2. I/O Mode:

The format of CWR in I/O mode is shown below-

The most significant bit (D7) is 1 for the I/O mode and 0 for the BSR mode.

D6 and D5 are used to select the mode as shown in diagram.

D4 is used to tell whether port A is taking input or displaying the result. If it is 1 then it is taking input otherwise displaying output.

D3 is used to tell whether port C higher bits is taking input or displaying the result. If it is 1 then it is taking input otherwise displaying output.

D2 tells the mode of port B. If it is 0 then port B is in m0 mode otherwise in m1 mode.

D1 is used to tell whether port B is taking input or displaying the result. If it is 1 then it is taking input otherwise displaying output.

D0 is used to tell whether port C lower bits is taking input or displaying the result. If it is 1 then it is taking input otherwise displaying output.